FPGAs for Software Defined Radio (SDR)

Radio was the first electronic application. When digital electronics came up and the World became flooded with digital gadgets, radio resisted and probably well deserves being referred to as the “last pure analog electronic application”. Many of us will inconciously associate ‘radio’ with music and news on the FM, but there is actually more, much more than that: Your satelite TV is a radio (yes, it receives radio waves), as it is your cell phone and the bluetooth in your wireless headphones and car hands-free or the Wi-Fi in your smartphone and router at home. Even your car fob has a tiny and smart radio that sends a changing key to your car every time. Plus the very specialized radios for industrial, scientific and military purposes.
All these new generations of ‘radio’ have a common characteristic: they all transmit digital data and not any longer analog audio signals. Even with a cell phone, since long ago, voice is digitized and sent as digital data. This brought almost a revolution in the modulation schemes. For radio waves to carry information, either analog or digital, a carrier waveform is modulated. For decades AM and FM were the predominant schemes. When digital data is broadcast, digital modulation methods are used and one could easily find and name twenty of them.
So many modulation schemes makes any hardware design to be short-lived and very narrow-oriented. It’s clearly the case where flexibility is needed but how to make, for example, an FSK (Frequency Shift Keying) receiver become a PSK (Phase Shift Keying) receiver? The key is to do most,if not all, of the radio operations (mixing, up and down converting, demodulating) in software with digitized values instead of in hardware with analog values. This is a Software Defined Radio: A radio system (receiver, transmitter or both, where some or most of the signal processing operations are not performed with physical analog magnitudes (voltages, currents) but with logical and mathematical operations on digitized values of the input signal.

 

Advantages of SDR

SDR is not simple or cheap, but complex and expensive. Is it worth? There a number of advantages pointing to SDR as being the future standard for radio systems:
Interoperability. An SDR can seamlessly communicate with multiple incompatible radios or act as a bridge between them. That was a primary reason for the US military’s interest in, and funding of, SDR for the past 30 years. Different branches of the military and law enforcement use dozens of incompatible radios, hindering communication during joint operations. A single multi-channel and multi-standard SDR can act as a translator for all the different radios.
Efficiency under varying conditions. An SDR can adapt the waveform to maximize a key metric. For example, a low-power waveform can be selected if the radio is running low on battery. A high-throughput waveform can be selected to quickly download a file. By choosing the appropriate waveform for every scenario, the radios can provide a better user experience.
Opportunistic frequency reuse (cognitive radio) An SDR can take advantage of underutilized spectrum. If the owner of the spectrum is not using it, an SDR can ‘borrow’ the spectrum until the owner comes back. This technique has the potential to dramatically increase the amount of available spectrum.
Reduced obsolescence (future-proofing). An SDR can be upgraded in the field to support the latest communications standards. This capability is especially important to radios with long life cycles such as those in military and space applications. For example, a new cellular standard can be rolled out by remotely loading new software into an SDR base station, saving the cost of new hardware and the installation labor.
Lower cost. An SDR can be adapted for use in multiple markets and for multiple applications. Economies of scale come into play to reduce the cost of each device. For example, the same radio can be sold to cell phone and automobile manufacturers. Just as significantly, the cost of maintenance and training is reduced.
Research and development. An SDR can be used to implement many different waveforms for real-time performance analysis. Large trade-space studies can be conducted much faster (and often with higher fidelity) than through simulations.

 

Basic hardware blocks of an SDR

Three main blocks form a Software Defined Radio: The analog fornt-end, the ADC (Analog to Digital Converter) and the Signal Processing (the FPGA or DSP). The front end usually contains an analog RF amplifier and an analog downconverter. This brings the RF signals down to a frequency that the ADC can handle, usually below 200 MHz. The ADC feeds the DDC (Digital Downconverter) stage, which used to be a monolithic chip but now is more frequently found in the FPGA. The diagram below shows a transceiver block diagram showing the front-end block (Flexible RF hardware), the ADC and DAC pair (as it is a receiver and transmitter) and the first processing stage (Channelization and Sample Rate conversion). The rest of processing is shown in the rightmost block.
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FPGAs: A new technology. A new mindset is needed.

It’s hard to keep up to date on FPGA technology, since new advancements are continually being made. The hottest features are soft processors, clocks up to 500 MHz and above, and lower core voltages to keep power and heat down. Also, dedicated hardware multipliers are now a common feature even in the cheapest models. High memory densities coupled with very flexible memory structures meet a wide range of data flow strategies. Logic slices with the equivalent of over ten million gates result from silicon geometries shrinking below 0.1 micron. BGA and flip-chip packages provide plenty of I/O pins to support on-board gigabit serial transceivers and other user-configurable system interfaces. To support such powerful devices, new design tools are appearing that now open up FPGAs to both hardware and software engineers. While in the very beginning logic equations and schematics were used, but later high level languages like Verilog or VHDL were and are used to described bigger and more complex designs. Simulation and modeling tools help to quickly analyze worst case propagation delays and suggest alternate routing strategies to optimize performance. A new industry of third party IP (Intellectual Property) core vendors now offer thousands of application-specific algorithms. These are ready to drop into the FPGA design process to help beat the time-to-market crunch and to minimize risk.

 

What makes FPGAs special for SDR?

All the logic elements in FPGAs can execute in parallel. This includes hundreds of hardware multipliers that can be on a single FPGA. This is in sharp contrast to programmable DSPs, which normally have just a handful of multipliers that must be operated sequentially. FPGA memory can now be configured with the design tool to implement just the right structure for tasks that include dual port RAM, FIFOs, shift registers and other popular memory types. These memories can be distributed along the signal path or interspersed with the multipliers and math blocks, so that the whole signal processing task operates in parallel in a systolic pipelined fashion. Again, this is dramatically different from sequential execution and data fetches from external memory as in a programmable DSP. FPGAs now have specialized serial and parallel interfaces to match requirements for high-speed peripherals and buses. As a result, FPGAs have significantly invaded the application task space split between general digital signal processors and ASICs. They offer the advantages of parallel hardware to handle some of the high process intensity functions like DDCs and the benefit of programmability to accommodate some of the decoding and analysis functions of DSPs. These advantages may come at the expense of increased power dissipation and increased product costs. However, these considerations are often secondary to the performance and capabilities of these remarkable devices.

 

Digital Downconverter (DDC) fundamentals

In recent times, the functions associated with DDCs have seen a shift from being done in ASICs to be done in FPGAs. For many applications, this implementation shift brings advantages like: design flexibility, higher precision processing, higher channel density, lower power, and lower cost per channel. With the advent of each new higher performance FPGA family, these benefits continue to increase. To understand how FPGAs play a key role in implementing DDCs that perform the function of a receiver, it’s important to break the DDC down into its individual functional blocks. The block diagram below shows a classic DDC.
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The first stage uses a complex digital mixer to translate the frequency of interest down to baseband. It uses a pair of multipliers and a DDS (Direct Digital Synthesizer) as the NCO (Numerically Controlled Oscillator). This function enables the user to tune the receiver to the desired frequency of interest. The second stage of the DDC reduces the sampling frequency of the signal to match the desired output bandwidth. It uses a CIC (Cascaded Integrator Comb) filter to decimate the data. A second CIC filter provides a coarse gain adjustment stage. The signal is then passed to a pair of additional polyphase filters. First a CFIR (Compensation Finite Impulse Response) filter then to a PFIR (Programmable Finite Impulse Response) filter. This filter pair provides additional decimation and final signal shaping prior to the rounding stage and final output. Most of these functions are implemented using multipliers. It thus becomes clear how the DDCs map into FPGAs. Most FPGAs include now a wealth of DSP function blocks which are primarily multipliers. The general purpose logic resource and on-chip memory of FPGAs also match the requirements of the DDC for implementing the required FIR filters and filter coefficient tables.
FPGAs continue to offer new possibilities and performance when addressing processing tasks like digital downconversion. With each new generation of higher performance FPGAs, processing precision continues to increase. This enables IP-based DDCs to outperform their ASIC-based cousins with specifications like better SFDR. It’s easy to understand how packing many channels of DDCs into one or two FPGAs can reduce the board count, power requirements and cost over a solution that requires 30 or 40 individual ASIC DDC chips. Additionally, FPGA solutions are extremely flexible since they can support vastly different signals with the simple loading of a different IP core while using the same hardware platform. But FPGA solutions are not always a perfect match for all requirements. They show the greatest advantages in systems with high channel densities and, typically, narrower bandwidths. In systems with just one or two channels and bandwidths in the range of 100 MHz or greater, the higher cost of the FPGAs needed can quickly exceed the cost of designing the system with a single multichannel DDC ASIC. Again, while cost, size and power are important factors in designing a receiver system, ultimately the technical requirements may require the choice of an ASIC or FPGA solution.

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